1. Field of the Invention
The present invention relates to a high precision oscillation circuit, and more particularly, to a high precision oscillation circuit which can control the effect of temperature variation upon frequency within a specific range.
2. Description of the Related Art
FIG. 1 shows a corresponding diagram of frequency variation versus voltage gain for a piezoelectric device. The piezoelectric device is usually used in a backlight module of an LCD monitor, and therefore its operating frequency will affect the brightness of the LCD monitor. As far as the analog circuit controls the piezoelectric device, the magnitude of the output circuit will affect the operating frequency of the piezoelectric device. Therefore, finding a method to control the output current of the analog circuit in order to insulate it from temperature variation is an important topic.
FIG. 2 is a prior art oscillation circuit, which includes an oscillation current generating stage 22 and an output current mirror 21. Generally speaking, due to the distortion of the current mirror caused by inconsistent working points of P1, P2 and P3 transistors and the mismatch of N2 and N3 transistors, the frequency of prior art oscillation circuit has 10% error at process corner SS (−40° C.), and 7% error at process corner FF (90° C.). Besides, prior art oscillation circuits usually embed the resistor R1 and capacitor C1 inside the analog chip, which causes the operating frequency to become more susceptible to temperature and process variation.
As far as the backlight control ICs that exist in the market are concerned, users usually request the effect of temperature variation upon frequency to be limited to a range of ±2%, and therefore prior art circuits do not fulfill the requirements of the current design trend any more.
FIGS. 3(a) and 3(b) show another prior art circuit design, which replicates the structure of transistors N2 and N3 to form transistors N2a and N3a in order to inversely offset current and frequency variation of the transistors N2 and N3 caused by temperature variation. However, the circuit designs of FIGS. 3(a) and 3(b) waste too much chip area and thus do not satisfy efficient design methodology.